Nowadays, power and energy consumption are two of the most important criterions in the design of on-chip applications. Other design constraints, such as performance, were dominant in the past, but now it is imperative to optimize for low power, since on-chip temperature and battery life are limiting design factors on modern multi/many core systems.
This lab explores different software and hardware approaches for power and energy reduction on modern embedded systems, considering other relevant metrics and constraints (e.g., temperature, performance, chip area).
|First Part: Software effects on Power and Performance
The first part of the lab consists of an exploration and analysis of the effect of loop transformation techniques and compiler optimizations in the power consumption, execution time and cache performance. SimpleScalar and Wattch simulators are used to run the applications and to obtain metrics to analyze
|Second Part: Hardware/Software Co-design
The second part of the lab consists of a Hardware/Software Co-design exploration using the High-Level Synthesis (HLS) technique. This technique takes a C code implementation and produces three types of system implementation: a complete hardware (RTL) implementation, a pure software implementation to be executed in a MIPS soft-processor, and a hybrid implementation where one or more functions of a program are compiled to hardware accelerators with the remaining program segments running in software in a MIPS soft-processor.
|Third Part: Demo in Thermal Lab
As part of the course, there will be access to the CES thermal lab, in which an experiment will be carried out to analyse the effect of power and temperature on a real board setup, using a thermal camera.